a) Field of the Invention
The present invention relates to a resin molded semiconductor device, and more particularly to a semiconductor device capable of suppressing generation of cracks to be caused by thermal stress at a peripheral area of a semiconductor chip.
b) Description of the Related Art
Common problems associated with resin molded semiconductor devices whose chips are resin-molded, are a shift of wiring patterns and generation of cracks in a passivation film to be caused by thermal stress generated by a difference of thermal expansion coefficients between semiconductor chips and sealing resin.
The surface of a semiconductor chip is generally divided into an inner pattern region where wiring patterns and functional elements such as transistors and resistors are formed, a bonding pad region outside the inner pattern region where bonding pads are disposed, and a reserved region from the outer periphery of the bonding pad region to the chip periphery.
In order to suppress a shift of wiring patterns and generation of cracks in a passivation film to be caused by thermal stress of the semiconductor chip, it has been proposed to form slits in a wiring pattern or form dummy wiring patterns. Most of conventional methods form such crack preventing structures in the inner pattern region.
FIG. 6 is a partial plan view showing an example of the layout of a semiconductor chip. At the outside area of a hatched inner pattern region b, a bonding pad region a is disposed which has a plurality of bonding pads a1 to a5. The bonding pad region a has an area from the outer periphery of the inner pattern region to the line extending through the outer sides of the bonding pads. Each bonding pad is a rectangle having a side length of, for example, about 100 .mu.m.
An area from the outer periphery of the bonding pad region to the outer periphery of the semiconductor chip is a reserved region c where no circuit element is formed. The reserved region has a width of 20 .mu.m to 100 .mu.m and is used for preventing cracks at a scribed surface from entering into the inner pattern region containing functional elements, when the wafer is diced into chips.
FIG. 7 shows an example of a cross sectional structure of a semiconductor chip, showing a portion from a bonding pad to a chip periphery. Formed on the surface of a semiconductor substrate 1 are a field oxide film 2, a first interlayer insulating film 3, and a first wiring layer 4 on the first interlayer insulating film 3. The first wiring layer 4 forms a bonding pad 4a and a metal seal ring pattern 4c. On the surface of the first wiring layer 4, a second interlayer insulating layer 5 and a passivation film 8 of SiN.sub.x are formed. The second interlayer insulating layer 5 is a laminate of a pair of plasma CVD SiO.sub.2 films 5a and 5b and a spin-on-glass (SOG) film 6 sandwiched therebetween. In the inner pattern region, a second wiring layer is formed on the second interlayer insulating layer 5 and is covered with the passivation film 8. The surface of the passivation film 8 is sealed with a resin region 9 used for sealing the semiconductor chip.
Many semiconductor devices have a multi-layer structure with a plurality of wiring layers and interlayer insulating layers. If the surface of an underlying layer is uneven, the precision of photolithography is lowered and step coverage of a higher level wiring layer becomes bad so that breakage of wiring layers or other defects are likely to occur. For planarization of the surface of an underlying layer, an SOG film effective for planarization is often used as part of an interlayer insulating layer. If the SOG film alone is used, moisture becomes easy to invade. An interlayer insulating layer including an SOG film between a pair of CVD insulating films is used in most cases.
An SOG film is formed by spin-coating liquid material over the substrate and thereafter heating it. The liquid material may be organic silane containing source material dissolved by solvent or a mixture of SiO.sub.2 particles and binder.
The liquid SOG film source material fills a recess in the underlying layer and planarizes the surface. The quality of an SOG film as an insulating film is not good. Therefore, the SOG film may be etched back by setting the etching rates of the SOG film and the underlying layer equal to each other. With this etch-back, the SOG film is left only at the recess, and the other SOG film on the upper flat surface of the stepped underlying layer is removed.
Spin-coated SOG film source material becomes thick and stagnant in a broad area because of a dam formed by the metal seal ring pattern at the chip peripheral area. Even after the etch-back, the SOG film is left in the broad area of the chip peripheral area. If a semiconductor device with such an SOG film is subjected to heat cycle tests, for example, in a temperature range from 150.degree. C. to minus 65.degree. C. about 500 to 1000 times, the interfaces between the broadly stagnant SOG film and CVD insulating films are stripped or peeled off, and therefore cracks are likely to be generated in the SOG film.
FIG. 8 is a diagram sketched from an enlarged photograph of an SOG film cross section of a semiconductor device after heat cycle tests. An SOG film 6 is flaked at either an interface to an upper plasma CVD SiO.sub.2 film 5b or to a lower one 5a, and cracks are formed in the SOG film 6.
Cracks are easy to be formed in the SOG film at the reserved region c (refer to FIG. 6) of a semiconductor chip. Cracks are easy to be formed particularly near at the corners of a semiconductor chip where more stress is likely to be applied.
Cracks formed in the SOG film at the reserved region c often induce generation of cracks reaching the inner pattern region b. Moisture may enter from these cracks. If moisture enters further the inner pattern region b, the characteristics of functional elements such as transistors are adversely affected. For example, if moisture reaches an oxide film, H.sup.+ ions enter the oxide film. If these H.sup.+ ions reach the gate oxide film, the threshold value of the transistor may vary, or if they reach near the lower interface of the field oxide film, negative charges may be induced in a p-type well, forming an n-type channel. Entered moisture often corrodes electrode material such as Al. Cracks formed in the SOG film may break a higher level wiring pattern.